Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in processor and system design require dynamic random access memory devices with high density, low power and fast access time for main memory. These memory devices must operate consistently over a range of physical parameters such as voltage and temperature. Moreover, these memory devices are subject to a statistical range of device parameters inherent in the manufacturing process such as variations in transistor gate length, gate oxide thickness and threshold voltage. These variations result in a distribution of memory devices having different speed and power characteristics. This is a significant design problem because slow device operating conditions, such as low voltage or high temperature, are limited by maximum access time or minimum circuit speed requirements. Alternatively, fast device operating conditions, such as high voltage or low temperature, are limited by maximum power consumption.
Previous memory circuits have employed special delay circuits to compensate for variations in physical parameters as disclosed by U.S. Pat. No. 5,068,553, incorporated herein by reference, wherein a polycrystalline silicon resistor and a capacitor generate a circuit delay having a reduced supply voltage dependence. Application of this circuit, however, is limited to delay circuits. Moreover, it fails to compensate for variations in device characteristics. Thus, the problem of significant distribution of memory devices having different device speed and power characteristics due to variations in physical and device parameters remains unresolved.